(a) Field of the Invention
The invention relates to an apparatus and method for driving a plasma display panel (PDP), and more particularly, a driver circuit which includes a power recovery circuit.
(b) Description of the Related Art
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images and includes, according to its size, more than several scores to millions of pixels arranged in a matrix pattern. PDPs may be classified as a direct current (DC) type or an alternating current (AC) type based on the structure of its discharge cells and the waveform of the driving voltage applied thereto.
DC PDPs have electrodes exposed to a discharge space to allow a DC to flow through the discharge space while the voltage is applied, and thus require a resistance for limiting the current. AC PDPs have electrodes covered with a dielectric layer that forms a capacitance component to limit the current and protects the electrodes from the impact of ions during a discharge. Thus, AC PDPs generally have longer lifetimes than DC PDPs.
One side of the AC PDP has scan and sustain electrodes formed in parallel, and the other side of the AC PDP has address electrodes perpendicular to the scan and sustain electrodes. The sustain electrodes are formed in correspondence to the scan electrodes and have the one terminal coupled to the one terminal of each scan electrode.
The method for driving the AC PDP generally includes a reset period, an addressing period, a sustain period, and an erase period in temporal sequence.
The reset period is for initiating the status of each cell so as to facilitate the addressing operation. The addressing period is for selecting turn-on/off cells and applying an address voltage to the turn-on cells (i.e., addressed cells) to accumulate wall charges. The sustain period is for applying sustain pulses and causing a sustain-discharge for displaying an image on the addressed cells. The erase period is for reducing the wall charges of the cells to terminate the sustain-discharge.
The discharge spaces between the scan and sustain electrodes and between the side of the PDP with the address electrodes and the side of the PDP with the scan and sustain electrodes act as a capacitance load (hereinafter, referred to as “panel capacitor”). Accordingly, capacitance exists on the panel. Due to the capacitance of the panel capacitor, there is a need for a reactive power to apply a waveform for the sustain-discharge. Thus, the PDP driver circuit includes a power recovery circuit for recovering the reactive power and reusing it. One power recovery circuit is disclosed in U.S. Pat. Nos. 4,866,349 and 5,081,400, issued to Weber, et al. (herinafter “Weber”).
The circuit disclosed in Weber repeatedly transfers the energy of the panel to a power recovery capacitor or the energy stored in the power recovery capacitor to the panel using a resonance between the panel capacitor and the inductor. Thus, the circuit's effective power is recovered. In this circuit, however, the rising time and the falling time of the panel voltage are dependent upon the time constant LC determined by the inductance L of the inductor and the capacitance C of the panel capacitor. The rising time of the panel voltage is equal to the falling time because the time constant LC is constant. For a faster rising time of the panel voltage, the switch coupled to the power source has to be hard-switched during the rise of the panel voltage, in which case the stress of the switch increases. The hard-switching operation also causes a power loss and increases the effect of electromagnetic interference (EMI).